This calendar provides the main topics covered during each lecture (L), assignment due dates, quiz dates, and recitation dates (R).
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| WEEK # | | | | DAY 1 | | | | DAY 2 | | | | DAY 3 | | | | DAY 4 | |
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| | | | | | | | | | 1 | | | | | | | | | | | | L1 - Course Overview and Mechanics. Basics of Information | | | | R1 | | | | | | | | | | | | | | | | | | | | | 2 | | | | L2 - Digital Abstraction, Combinational Logic, Voltage-Based Encoding | | | | R2 | | | | L3 - CMOS Technology; Power and Performance Issues | | | | R3 | | | | | | | | | | | | | | | | | | | | | 3 | | | | L4 - Design of Logic Gates; Timing | | | | R4 | | | | L5 - Canonical Logic Forms, Synthesis, Simplification Lab #1 Due | | | | R5 Quiz #1 | | | | | | | | | | | | | | | | | | | | | 4 | | | | L6 - Storage Elements, State, Finite State Machine | | | | R6 | | | | L7 - D-registers, FSM Example Lab #2 Due | | | | R7 | | | | | | | | | | | | | | | | | | | | | 5 | | | | L8 - Synchronization, Metastability | | | | R8 | | | | L9 - Pipelining; Throughput and Latency Lab #3 Due | | | | R9 | | | | | | | | | | | | | | | | | | | | | 6 | | | | L10 - Case Study: Multipliers | | | | R10 | | | | L11 - Models of Computation, Programmable Architectures | | | | R11 Quiz #2 | | | | | | | | | | | | | | | | | | | | | 7 | | | | | | | | R12 | | | | L12 - Beta Instruction Set Architecture, Compilation Lab #4 Due | | | | R13 | | | | | | | | | | | | | | | | | | | | | 8 | | | | L13 - Machine Language Programming Issues | | | | R14 | | | | L14 - Stacks and Procedures | | | | R15 | | | | | | | | | | | | | | | | | | | | | 9 | | | | L15 - Non-Pipelined Beta Implementation | | | | R16 | | | | L16 - Pipelined Beta Implementation, Bypassing | | | | R17 Quiz #3 | | | | | | | | | | | | | | | | | | | | | 10 | | | | L17 - Pipeline Issues: Delay Slots, Annulment, Exceptions | | | | R18 | | | | L18 - Multilevel Memories; Locality, Performance, Caches Lab #5 Due | | | | R19 | | | | | | | | | | | | | | | | | | | | | 11 | | | | L19 - Case Study: Cache Design | | | | R20 | | | | L20 - Communication Issues: Busses, Networks, Protocols | | | | R21 Quiz #4 | | | | | | | | | | | | | | | | | | | | | 12 | | | | L21 - Virtual Memory: Mapping, Protection, Contexts | | | | R22 | | | | L22 - Virtual machines, OS Kernel Code, Supervisor Calls, Scheduling Lab #6 Due | | | | R23 | | | | | | | | | | | | | | | | | | | | | 13 | | | | L23 - Communicating Processes: Semaphores, Synchronization, Atomicity, Deadlock | | | | R24 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 14 | | | | L24 - Interrupts, Real Time | | | | R25 | | | | L25 - Parallel Processing, Shared Memory, Cache Coherence, Consistency Criteria | | | | R26 Quiz #5 | | | | | | | | | | | | | | | | | | | | | 15 | | | | L26 - Looking Ahead: Future Computer Architectures | | | | Lab #7 Due | | | | | | | | | | | | | | | | | | |
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