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Calendar / Schedule



Calendar

The calendar below provides information on the lecture (L), recitation (R), and tutorial (T) sessions for the course.

SES #TOPICSKEY DATES
R1Diagnostic Review: First Order Differential Equations; One-dimensional Electrostatics; Linear Equivalent Circuits and Linear Circuit Analysis.
L1Introduction. Intrinsic Semiconductors, Bond Structure, Holes and Electrons; ni(T). Dopants - Donors and Acceptors. no and po in Extrinsic (Doped). Sic: Thermal Equilibrium, Detailed Balance, nopo Product; no, po Given NA, ND.
R2Calculations of no, po in Variously Doped Examples to Review "no, po given NA, ND" from lecture. Drift, Basic Concepts: Net Velocity vs. Field, Mobility; Conductivity, Resistivity. Concept of n-type and p-type.PS #1 Out
T1Review of Electrostatics (8.02) and Poisson's Equation; ρ, Ε, Φ; Parallel Plate Capacitors. Doping and Carrier Type Issues as Needed.
T1/L2Review of Electrostatics (8.02) and Poisson's Equation; ρ, Ε, Φ; Parallel Plate Capacitors. Doping and Carrier Type Issues as Needed (contd.)

Uniform Excitations: Uniform Electric Field and Drift (Review from Rec. 2). Uniform Optical Injection. Low Level Injection. Minority Carrier Lifetimes. Homogeneous Solution.
R3Typical Values of Mobility, Conductivity, Resistivity. Comparison with Metals, Insulators. Population Transients. Responses to Various Common Waveforms. Analogy with RC Circuits.
L3Non-uniform Injection and/or Doping. Diffusion. Continuity/Conservation. The Five Basic Equations.
R4Complete Discussion of Optical Injection. Diffusion Video. Haynes-Shockley Video.PS #1 Due

PS #2 Out
T2Population Transient Problems. Identification of Simple Situations as Special Cases of the Five Basic Equations.
L4Linearization and Decoupling of 5 Basic Equations in Flow Problem Regime: Quasineutrality, Debye Length, LDx, and Dielectric Relaxation Time, τD; Minority Carrier Flow by Diffusion. Diffusion Equation(s) for n': General Solutions; Boundary Conditions; Procedure to find n, p, Je, Jh, Ex having n'.
R5Boundary Conditions for Flow Problems: Ohmic Contacts, Reflecting Surfaces, Continuity at Internal Boundaries. Example of Injection in middle of a Bar; Short-base and Long-base Limits.
L5Non-uniformly Doped Material in Thermal Equilibrium. Electrostatic Potential (Using Einstein Relation); Poisson equation. no(x), po(x), Φ(x) when Doping Varies Slowly; Quasi-neutral Approximation; Extrinsic Debye Length, LDx. Begin Abrupt p-n Junction.
R6Review Concepts in L5. Typical values of Φn, Φp; Emphasize Weak Dependence on no, po; 60 mV/decade Rule. Look no, po, and Φ's in Vicinity of an Abrupt p-n Junction. More (Final) Discussion and Solutions of Flow Problems as needed.PS #2 Due

PS #3 Out
T3More (Final) Discussion of Flow Problems, Boundary Conditions, and Solutions. Long Diffusion Length (Infinite Lifetime) approximation; Integral Solutions, Nature of Profiles. Electrostatic Potential of Various Metals and Semiconductors, and Consideration of Φ(x) around a Circuit and through Contacts in T.E.
L6Abrupt p-n Junction in Thermal Equilibrium; the Depletion Approximation. Expressions for W, xn, xp, Epk, Φb. Extension of Model to Biased Junctions: Argue can Replace Φb by (Φb - vA) if Charge Due to Currents Can be Neglected and All vA Appears across Junction.
R7Review Depletion Approximation Model for Junction and the Effect of Bias; Comment on Φ(x) around a circuit through Contacts. Charge Store associated with SCL and Depletion Capacitance.
L7Forward Biased Abrupt p-n Junction. Carrier Equilibrium with/across Space Charge Layer; Current Flow. Derivation of I-V Expression. Plots of Carrier Populatioins through Forward and Reverse Biased Short Base p-n Diodes (Empahisize Injection is into Lightly Doped Side).
R8Charge Storage Associated with Minority Carrier Injection; Diffusion Capacitance.PS #3 Due

PS #4 Out
T4Examples of Graded Junction Profiles as a way of Reinforcing Understanding of the Depletion Approximation and the Electrosatics of p-n Junctions.
T4/L8Examples of Graded Junction Profiles as a way of Reinforcing Understanding of the Depletion Approximation and the Electrosatics of p-n Junctions (contd.)

Review Diodes Current, and QN Region Excess Charge Stores and Diffusion Capacitance; Introduce BJT Structure, and Bipolar Junction Transistor (BJT) Operating Principles; Derive Currents for npn BJT in Forward Active Region; Introduce Base and Emitter Defects.
R9Review of BJT Issues, Focusing on Reverse Biased CB Diode and Impact of Carrier Injection toward it. Schematic Symbols for BJTs and Example Inverter/Amplifier Circuits; Compare to MOSFET from 6.002; Discuss two Viewpoints: Base-emitter Voltage and Base Current as Controlling Collector Current.
L9Superposition, Ebers-Moll Model for npn. Expressions for α and β. Large Signal BJT Characteristics and Models: Regions of Operation; Approximate Model Valid in Forward Active Region. β-model. Discussion of Limitations of Model and Extremes of Operation; Non-ideal Elements.
R10Complete Discussion of Large Signal BJT Models. Use Large Signal BJT Model to Calculate Transfer Characteristic of Common Emitter Amplifier.PS #4 Due

PS #5 Out
T5Plots of Carrier Populations and Current Densities Through BJTs in Various Operating Regions Review of Material to Date in Preparation for First Exam.
T5/L10Plots of Carrier Populations and Current Densities Through BJTs in Various Operating Regions Review of Material to Date in Preparation for First Exam (contd.)

Other Junction Devices (a Disguised Quiz Review): LEDs, Illuminated p-n Diodes; Superposition Solar Cells and Photodiodes.
No Formal Recitation Sessions. Instructors will be available to answer questions and Review Issues for the Quiz.
Q1Closed Book. Covering Material through R8 and PS #4 (i.e., through p-n Diodes).
L11MOS Structures. Discussion of Accumulation, Depletion, Inversion. Application of Depletion Approximation to MOS Capacitor to Relate Channel Charges to Gate Voltage. Flat Band Voltage; Threshold Voltage.
R11Review Accumulation, Depletion, and Inversion in MOS, and Model Relating Channel Charge to Gate Voltage in Excess of Threshold. C-V Relationship for MOS Structure.PS #5 Due

PS #6 Out
T6Discussion of MOS Structure and MOS Capacitor Issues.
L12Gradual Channel Approximation for MOSFET i-v Characteristics; Quadratic Approx. Discussion of Pinch-off. Regions of Operation.
R12Review of Gradual Channel Model. Features of Characteristics. Possible MOSFET Device Types: n- and p-channel, Enhancement and Depletion Mode.
L13Summary of Static Large Signal BJT and MOSFET Models. Enhancements: Base Width/Channel Length Modulation (Early Effects); Charge Stores (diffusion and Depletion Stores in BJTs and MOSFETs).
R13Complete Discussion of MOSFET Modeling. Use of Large Signal Model to Calculate Transfer Characteristics of Common-source Inverter with Resistor Pull-up.PS #6 Due

PS #7 Out
T7MOSFET Models, Large and Small Signal, for n- and p Channel Devices, Enhancement and Depletion Mode.
T7/L14MOSFET Models, Large and Small Signal, for n- and p Channel Devices, Enhancement and Depletion Mode (contd.)

Incremental Models for BJT (Hybrid-π) and MOSFET. npn vs. pnp; n-channel vs. p-channel; go, Early Voltage; Capacitances. Importance of Stable Bias Point.
R14Review Incremental Models, Including Diodes. Establishing a Stable Bias Point Using Current Sources in Source/Emitter Circuit. Current Source Design.
L15Basic Inverters as Building Blocks for Digital Logic, Memory; Performance Critieria. Begin MOS Logic; Inverter Options; Why CMOS.
R15Discuss Calculation of MOSFET Inverter Transfer Characteristics; Working of Specific Examples (Saturated n-MOS Pull-up, CMOS)PS #7 Due

PS #8 Out
T8HSPICE for p-n Diodes, BJTs, and MOSFETs. (HSPICE Sessions in Electronic Classroom.)
T8/L16HSPICE for p-n Diodes, BJTs, and MOSFETs. (HSPICE Sessions in Electronic Classroom) (contd.)

CMOS in All its Glory: Comparison of Various Loads in Logic Context - Logic Swing, Speed, Power, Manufacturablity. Memory Cells.
R16Final CMOS Comments. Begin Linear Amplifiers by Doing Analysis of Simple Resistor-loaded Common-emitter Amplifier and Discussing: Using the Large Signal Model to Determine Bias Point, Evaluating the Parameters in the Incremental Model, and Calculating Mid-band Gain
L17Begin Transistor Amplifiers; Common-source as Example. Performance Metrics: Voltage, Current, and Power Gains; Input and Output Resistances. Concept of Mid-band Frequency Range.
R17Common-source and Common-emitter Amplifiers with Current Source Loads.PS #8 Due

PS #9 Out
T9Review in Preparation for Second Exam.
T9/L18Review in Preparation for Second Exam (contd.)

Basic Single Transistor Amplifier Stages. Common-base/-Gate and Emitter-/Source-Follower Amplifier Stages. Degenerate-Emitter/-Source Stages; Analysis and Features. Two-port Models.
No formal Recitation Sessions. Instructors will be available to answer Questions and Review Issues for the Quiz.
Q2Closed Book. Covering Material through R16 and PS #8.
L19Differential Amplifiers: Large Signal Analysis and Transfer Characteristics; Incremental Analysis and Half-circuit Analysis Techniques.
R18Discuss Differential Amplifier Issues: Biasing and Current Source Circuits; Examples of Small Signal Analysis Using Half-circuit Techniques and Importance of Knowing Single Transistor Stages.Design Problem Out
R19Overview of Design Problem Circuit. Understanding the Performance Specifications. General Approach to Analysis.PS #9 Due
L20Complete General Differential Amplifiers. Current-source Biasing Circuits. Achieving Maximum Gain while Staying in Forward Active Region: Resistor Loads, Non-linear Loads.
R20More Discussion of Differential Amplifier Issues Relevant to, and in the Context of, the Design Problem.
T10Design Problem Discussion.
L21Active Loads: Lee Load; Current Mirror Loads; Double- to Single-ended Output Conversion. Multi-stage Amplifiers; Issues of Bias, Loading, Stage Choice. Applications and Advantages of CMOS.
R21Continued Consideration of Multi-stage Differential Amplifiers. Calculation of Input and Output Resistances. Determination of Common- and Difference-mode Voltage Swings.
L22Bounding Mid-band; Methods of Open- and of Short-circuit Time Constants in High Frequency Analysis of Multi-stage Amplifiers. High Frequency Gain of Common-emitter/-Source Stage; Miller Capacitance.
R22General Miller Capacitance Phenomenon. Lack of Miller Capacitance in Common-gate/-Base and Followers. Final Design Problem Comments.
T11Discussion of Design Problem Issues.
T11/L23Discussion of Design Problem Issues (contd.)

A Look at the a Commercial Op-amp Design (741?); Use to Discuss Some Special Stages (Darlington, Cascode, Push-Pull, etc.) Use of Capacitor to Stabilize Circuit. Expand upon Cascode as Important Multi-transistor Stage: Large Output Resistance, Excellent High Frequency Performance.
R23IC Fabrication Technology; Berkeley CMOS Fabrication Video.Design Problem Due

PS #10 Out
L24

Intrinsic Limits to High Frequency Performance of MOSFETs and BJTs: wα, wβ, wt. Limits of Quasi-static Approx.

R24High Frequency Analysis. Method Of Open-circuit Time Constants; OCTC Example.
L25CMOS Gate Delay and Power Estimates; Relation to Device Dimensions. Scaling Rules. Example of Scaling: 386/486/Pentium.
R25Complete Discussion of Scaling. Driving Signals Off-chip; Digital Buffer Ideas, Issues, and Design.PS #10 Due
T12Discussion of Design Problem Solution, and Consideration of the High Frequency Performance of the Circuit.
L26Overview of the IC Industry, Analog and Digital. Review of Course and Suggestions for Follow-on Subjects.
R26Course Review and Wrap-up.
Final Exam. Closed Book. Covering all Material in Subject.

 








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