Contents of this page courtesy of Francis A. Honore. Used with permission.
PAL Programming
Verilog® Simulation
Creating and Simulating RAM
ROM Initialization
PROM Tools
Cypress WARP is a tool for generating PAL programming data. WARP takes a design in Verilog® and produces a JEDEC (.jed) programming file to be used by the PAL burners.To use WARP on the Lab PC, launch the application by clicking on the Galaxy desktop icon. Galaxy is the graphical front end to WARP. For instructions on using WARP, refer to theWARP Tutorial. (PDF)
Once a .jed file is created, it needs to be transferred to the PAL programming station to be burned into the PAL. For instructions on using the PAL programmer, view the PAL Programmer Guide. (PDF)
Altera FPGA Programming
The two phases for generating a programming file for the Altera FPGA's can be split between simulation/verification of the Verilog® hardware description followed by synthesis/optimization. Modelsim will be used for simulating the Verilog® description of the system to be built. Altera's MAX+plusII tool performs the final phase of mapping the Verilog® description to the device. MAX+plusII also has a built-in simulator.
On the Lab PC under Windows® XP, launch ModelSim from the Desktop icon (or Start -> All Programs -> ModelSim SE -> ModelSim)
On a Sun workstation, you must first configure your environment correctly. Then run 'vsim &' to start the application.
Create a new project with: File->New->Project and a wizard walks you through project creation.
For examples of using Modelsim for Verilog® simulation, refer to the Modelsim tutorial. (PDF)
Creating and Simulating RAM in ModelSim
Refer to this guide to generate memories in MAX+plusII and simulate in Modelsim. (PDF)
Generating ROM Data for MAX+plusII
When generating an internal ROM in an Altera FPGA, the memory contents can be specified in a Memory Initialization File (.mif). The format is shown here and also available (rom8x8.mif (MIF)) as a starting point. This file is used with the Megawizard Plug-in Manager to create a ROM module to instantiate in a design.
-- MEMORY INITIALIZATION FILE
-- EXAMPLE DATA FOR AN 8x8 ROM
WIDTH = 8; % WIDTH OF OUTPUT IS REQUIRED, ENTER A DECIMAL VALUE %
DEPTH = 8; % DEPTH OF MEMORY IS REQUIRED, ENTER A DECIMAL VALUE %
ADDRESS_RADIX = HEX; % Address and data radixes are optional, default is hex %
DATA_RADIX = HEX; % Valid radixes = BIN,DEC,HEX or OCT %
CONTENT BEGIN
0 : 07; % ADDRESS : VALUE %
1 : 06;
2 : 05;
3 : 04;
4 : 03;
5 : 02;
6 : 01;
7 : 00;
END;
-- SHORTCUTS FOR SPECIFYING CONTENTS
-- [0..FF] : 0; % Range--Every address from 0 to FF = 0%
-- D : 7; % Single address--Address D = 7 %
-- 6 : 9 C 8; % Range starting from specific address--%
-- If there are multiple values for the same address only the last value is used
To generate a ROM module using this example in MAX+plusII:
There are a suite of command line tools available for generating data to be stored in PROM chips. These tools are only needed for final projects which, for example, may use PROMs for storing character or image data. A promtools guide provides further details.
Dat2ntl is a command line routine for generating a .hex (.ntl) file which is also suitable for MAX+plusII ROM initialization.
Create a .dat file following the example in impulses.dat. (DAT) Convert to the Intel Hex Format: 'dat2ntl impulses.dat impulses.ntl'.
Refer to the dat2ntl manpage for further details. (PDF)