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Introductory Digital Systems Laboratory >> Content Detail



Calendar / Schedule



Calendar

The calendar below provides information on the course's lectures (L), recitations (R), and project (P) sessions. The last lecture or recitation is delivered 5 weeks before the end of the semester; after that date, class time is spent entirely on the final project.

SES #TOPICSKEY DATES
L1Introduction

Course Objectives, Digital Logic, Hardware Description Languages

Logic Analyzer Demos in the Lab by TAs
Problem Set 1 Out

Lab 1 Out
L2Combinational Logic

Logic Gates, Boolean Algebra, Visualizations of Boolean Algebra, Hazards

Logic Analyzer Demos in the Lab by TAs (cont.)
L3Introduction to Verilog® (Combinational Logic)

Logic Synthesis, The Verilog® Hardware Description Language, Combinational Logic in Verilog®, Testbenches
L4Sequential Building Blocks

Preserving State with Feedback, Latches and Flip-flops, Clocks and Timing Constraints, Clock Skew

WARP, MAX+plus II, and ModelSim Demos in the Lab by TAs
L5Simple Sequential Circuits and Verilog®

Simple Counters, Verilog® Implementation of Sequential Circuits

WARP, MAX+plus II, and ModelSim Demos in the Lab by TAs (cont.)
Problem Set 1 Due
L6Finite-State Machines and Verilog® Implementation

Metastability and Synchronization, Mealy and Moore Formalisms, Verilog® Implementations, FSM Examples
Problem Set 2 Out

Lab 2 Out
R1Lab 2 Discussion and DemonstrationLab 1 Checkoff

Lab 1 Report Due
L7Memories

Technologies, Types of RAM and ROM, Memory Controller Circuits, Specialty Memories, High-performance Interfaces
L8Circuits for Arithmetic

Binary Addition and Subtraction, Implementation and Performance of the Full Adder, High-speed Addition, Signed Arithmetic
R2RecitationProblem Set 2 Due
L9Analog Building Blocks

Analog Inputs, Useful Op-amp Circuits, A/D and D/A Conversion, Useful A/D and D/A Circuits
L10System Integration Issues and Major/Minor FSM

Hierarchy and Modularity, Data and Control Paths, Major and Minor FSMs, Memory Modules (RAM/ROM) in Altera, Design Tips

Lab 3 Overview
Problem Set 3 Out
R3RecitationLab 2 Checkoff
L11Reconfigurable Logic

Overview of Commercial Devices, Programmable Logic (PAL), FPGA Architectures, and Software Tools
Lab 2 Report Due

Lab 3 Out
L12Reconfigurable Logic (cont.)

Overview of Commercial Devices, Programmable Logic (PAL), FPGA Architectures, and Software Tools
R4Recitation
L13Video

Displays, Synchronization, Recovery of Signals, Sync Timing
L14Project Kickoff

Video of Past 6.111 Projects, Project Ideas, Deadlines and Goals, Project Guidelines, Grading, Asynchronous Interfaces and Kit-to-kit Communication
No RecitationLab 3 Analog Checkoff

Problem Set 3 Due
L15Digital Integrated Circuits and Systems

Moore's Law, VLSI Integration, Layout and Fabrication, Application-specific Circuits, Microprocessors. Behavioral and Algorithmic Transformations, Retiming, Parallelism and Pipelinling
Special Quiz Review by TAs

Formation of Project Teams
R5Recitation
L16Power Dissipation

Heat and Battery Life Issues, Sources of Power Dissipation, Circuit and Algorithm Optimizations for Power, Voltage Scaling
Project Abstracts Due

Lab 3 Checkoff

Lab 3 Report Due
L17Motors and Position Determination

Servos, Position Measurement, Encoders, Motors, Windings

Project Proposals for Proposal Conference Due
P1Proposal Conference with TAsLab 2 Revised Report Due (part of the MIT undergraduate communication requirement)

Project Proposals for Proposal Conference Due
P2Block Diagram Conference with TAs
P3Block Diagram Conference with TAs (cont.)
P4Block Diagram Conference with TAs (cont.)
P5Project Design PresentationsEta Kappa Nu ("HKN") Review

Customized Project Checklist Due
P6Project Design Presentations (cont.)
P7Project Design Presentations (cont.)
P8Project Design Presentations (cont.)
P9Implement/Debug
P10Implement/Debug (cont.)
P11Implement/Debug (cont.)
P12Implement/Debug (cont.)
P13Implement/Debug (cont.)
P14Final Project DemonstrationsFinal Project Report Due (three days after session P13)

 








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